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ST STM32F446 Series Reference Manual page 174

Advanced arm-based 32-bit mcus

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Reset and clock control (RCC)

Addr.

Register

offset

name

RCC_AHB1

LPENR

0x50

Reset value

RCC_AHB2

LPENR

0x54

Reset value

RCC_AHB3

LPENR

0x58

Reset value

Reserved

0x5C

Reset value

RCC_APB1

LPENR

0x60

Reset value

RCC_APB2

LPENR

0x64

Reset value

Reserved

0x68

Reset value

Reserved

0x6C

Reset value

RCC_BDCR

0x70

Reset value

RCC_CSR

0x74

Reset value

0

174/1328

Table 21. RCC register map and reset values (continued)

1

1

1

1

1

1

1

1

1

1

0

0

0

1

1

1

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

RM0390 Rev 4

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

RM0390

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

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