Dcmi Status Register (Dcmi_Sr) - ST STM32F446 Series Reference Manual

Advanced arm-based 32-bit mcus

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DCMI status register (DCMI_SR)

Address offset: 0x04

Reset value: 0x0000 0000

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 FNE: FIFO not empty

This bit gives the status of the FIFO

1: FIFO contains valid data

0: FIFO empty

Bit 1 VSYNC:

This bit gives the state of the DCMI_VSYNC pin with the correct programmed

When embedded synchronization codes are used, the meaning of this bit is the

0: active frame

1: synchronization between frames

In case of embedded synchronization, this bit is meaningful only if the

CAPTURE bit in DCMI_CR is set.

Bit 0 HSYNC:

This bit gives the state of the DCMI_HSYNC pin with the correct programmed

When embedded synchronization codes are used, the meaning of this bit is the

0: active line

1: synchronization between lines

In case of embedded synchronization, this bit is meaningful only if the

CAPTURE bit in DCMI_CR is set.

RM0390 Rev 4

Digital camera interface (DCMI)

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