Table 34. Fifo Threshold Configurations - ST STM32F446 Series Reference Manual

Direct memory access controller (DMA)
FIFO threshold and burst configuration
Caution is required when choosing the FIFO threshold (bits FTH[1:0] of the DMA_SxFCR
register) and the size of the memory burst (MBURST[1:0] of the DMA_SxCR register): The
content pointed by the FIFO threshold must exactly match an integer number of memory
burst transfers. If this is not in the case, a FIFO error (flag FEIFx of the DMA_HISR or
DMA_LISR register) is generated when the stream is enabled, then the stream is
automatically disabled. The allowed and forbidden configurations are described in
The forbidden configurations are highlighted in gray in the table.
MSIZE
Byte
216/1328
Figure 29. FIFO structure

Table 34. FIFO threshold configurations

FIFO level MBURST = INCR4
1/4 1 burst of 4 beats
1/2 2 bursts of 4 beats
3/4 3 bursts of 4 beats
Full 4 bursts of 4 beats
RM0390 Rev 4
MBURST = INCR8
Forbidden
1 burst of 8 beats
Forbidden
2 bursts of 8 beats
RM0390
Table 34.
MBURST = INCR16
Forbidden
1 burst of 16 beats