Data Reception Management - ST STM32F446 Series Reference Manual

SPDIF receiver interface (SPDIFRX)
When SPDIFRXEN is set to 0, the IP is disabled, meaning that all the state machines are
reset, and RX_BUF is flushed. Note as well that flags FERR, SERR and TERR are reset.
27.3.6

Data reception management

The SPDIFRX offers a double buffer for the audio sample reception. A 32-bit buffer located
into the SPDIFRX_CLK clock domain (RX_BUF), and the SPDIFRX_DR register. The valid
data contained into the RX_BUF will be immediately transferred into SPDIFRX_DR if
SPDIFRX_DR is empty.
The valid data contained into the RX_BUF will be transferred into SPDIFRX_DR when the
two following conditions are reached:
•
The transition between the parity bit (P) and the next preamble is detected (this
indicated that the word has been completely received).
•
The SPDIFRX_DR is empty.
Having a 2-word buffer gives more flexibility for the latency constraint.
The maximum latency allowed is T
Where T
the period of PCLK1 clock, and T
The SPDIFRX offers the possibility to use either DMA (spdifrx_dma_req/clr_d) or interrupts
for transferring the audio samples into the memory. The recommended option is DMA, refer
to Section 27.3.10: DMA Interface
The SPDIFRX offers several way on handling the received data. The user can either have a
separate flow for control information and audio samples, or get them all together.
For each sub-frame, the data reception register SPDIFRX_DR contains the 24 data bits,
and optionally the V, U, C, PE status bits, and the PT (see
Note that PE bit stands for Parity Error bit, and will be set to 1 when a parity error is detected
in the decoded sub-frame.
The PT field carries the preamble type (B, M or W).
V, U and C are a direct copy of the value received from the S/PDIF interface.
The bit DRFMT allows the selection between 3 audio formats as shown in
908/1328
is the audio sampling rate of the received stereo audio samples, T
SAMPLE
- 2T - 2T
SAMPLE PCLK
is the period of SPDIFRX_CLK clock.
SPDIFRX_CLK
for additional information.
RM0390 Rev 4
SPDIFRX_CLK
Mixing data and control
Figure
RM0390
is
PCLK
flow).
349.