Table 97. Positioning Of Captured Data Bytes In 32-Bit Words (8-Bit Width); Table 98. Positioning Of Captured Data Bytes In 32-Bit Words (10-Bit Width); Figure 103. Dcmi Signal Waveforms - ST STM32F446 Series Reference Manual

Digital camera interface (DCMI)
1. The capture edge of DCMI_PIXCLK is the falling edge, the active state of DCMI_HSYNC and
DCMI_VSYNC is 1.
2. DCMI_HSYNC and DCMI_VSYNC can change states at the same time.
8-bit data
When EDM[1:0] in DCMI_CR are programmed to "00" the interface captures 8 LSBs at its
input (DCMI_D[0:7]) and stores them as 8-bit data. The DCMI_D[13:8] inputs are ignored. In
this case, to capture a 32-bit word, the camera interface takes four pixel clock cycles.
The first captured data byte is placed in the LSB position in the 32-bit word and the 4
captured data byte is placed in the MSB position in the 32-bit word.
example of the positioning of captured data bytes in two 32-bit words.

Table 97. Positioning of captured data bytes in 32-bit words (8-bit width)

Byte address
0
4
10-bit data
When EDM[1:0] in DCMI_CR are programmed to "01", the camera interface captures 10-bit
data at its input DCMI_D[0..9] and stores them as the 10 least significant bits of a 16-bit
word. The remaining most significant bits in the DCMI_DR register (bits 11 to 15) are
cleared to zero. So, in this case, a 32-bit data word is made up every two pixel clock cycles.
The first captured data are placed in the LSB position in the 32-bit word and the 2
captured data are placed in the MSB position in the 32-bit word as shown in

Table 98. Positioning of captured data bytes in 32-bit words (10-bit width)

Byte address
0
4
426/1328

Figure 103. DCMI signal waveforms

31:24 23:16
D [7:0] D
n+3 n+2
D [7:0] D
n+7 n+6
31:26 25:16
0 D
n+1
0 D
n+3
RM0390 Rev 4
15:8
[7:0] D [7:0]
n+1
[7:0] D [7:0]
n+5
15:10
[9:0] 0
[9:0] 0
RM0390
th
Table 97 gives an
7:0
D [7:0]
n
D [7:0]
n+4
nd
Table 98.
9:0
D [9:0]
n
D [9:0]
n+2