ST STM32F446 Series Reference Manual page 134

Reset and clock control (RCC)
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 CSSC: Clock security system interrupt clear
Bit 22 PLLSAIRDYC: PLLSAI Ready Interrupt Clear
Bit 21 PLLI2SRDYC: PLLI2S ready interrupt clear
Bit 20 PLLRDYC: Main PLL(PLL) ready interrupt clear
Bit 19 HSERDYC: HSE ready interrupt clear
Bit 18 HSIRDYC: HSI ready interrupt clear
Bit 17 LSERDYC: LSE ready interrupt clear
Bit 16 LSIRDYC: LSI ready interrupt clear
Bit 15 Reserved, must be kept at reset value.
Bit 14 PLLSAIRDYIE: PLLSAI Ready Interrupt Enable
Bit 13 PLLI2SRDYIE: PLLI2S ready interrupt enable
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This bit is set by software to clear the CSSF flag.
0: No effect
1: Clear CSSF flag
This bit is set by software to clear PLLSAIRDYF flag. It is reset by hardware when the
PLLSAIRDYF is cleared.
0: PLLSAIRDYF not cleared
1: PLLSAIRDYF cleared
This bit is set by software to clear the PLLI2SRDYF flag.
0: No effect
1: PLLI2SRDYF cleared
This bit is set by software to clear the PLLRDYF flag.
0: No effect
1: PLLRDYF cleared
This bit is set by software to clear the HSERDYF flag.
0: No effect
1: HSERDYF cleared
This bit is set software to clear the HSIRDYF flag.
0: No effect
1: HSIRDYF cleared
This bit is set by software to clear the LSERDYF flag.
0: No effect
1: LSERDYF cleared
This bit is set by software to clear the LSIRDYF flag.
0: No effect
1: LSIRDYF cleared
This bit is set and reset by software to enable/disable interrupt caused by PLLSAI lock.
0: PLLSAI lock interrupt disabled
1: PLLSAI lock interrupt enabled
This bit is set and cleared by software to enable/disable interrupt caused by PLLI2S lock.
0: PLLI2S lock interrupt disabled
1: PLLI2S lock interrupt enabled
RM0390 Rev 4
RM0390