Interrupt Flag Clear Register (Spdifrx - ST STM32F446 Series Reference Manual

Advanced arm-based 32-bit mcus

Hide thumbs Also See for STM32F446 Series:

Table of Contents

Interrupt flag clear register (SPDIFRX_IFCR)

Address offset: 0x0C

Reset value: 0x0000 0000

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 SYNCDCF: Clears the Synchronization Done flag

Writing 1 in this bit clears the flag SYNCD in the SPDIFRX_SR register.

Reading this bit always returns the value 0.

Bit 4 SBDCF: Clears the Synchronization Block Detected flag

Writing 1 in this bit clears the flag SBD in the SPDIFRX_SR register.

Reading this bit always returns the value 0.

Bit 3 OVRCF: Clears the Overrun error flag

Writing 1 in this bit clears the flag OVR in the SPDIFRX_SR register.

Reading this bit always returns the value 0.

Bit 2 PERRCF: Clears the Parity error flag

Writing 1 in this bit clears the flag PERR in the SPDIFRX_SR register.

Reading this bit always returns the value 0.

Bits 1:0 Reserved, must be kept at reset value.

SPDIF receiver interface (SPDIFRX)

RM0390 Rev 4

Chapters

Table of Contents

Do you have a question about the STM32F446 Series and is the answer not in the manual?