ST STM32F446 Series Reference Manual page 204

Advanced arm-based 32-bit mcus

Hide thumbs Also See for STM32F446 Series:

Table of Contents

Direct memory access controller (DMA)

Independent source and destination transfer width (byte, half-word, word): when the

data widths of the source and destination are not equal, the DMA automatically

packs/unpacks the necessary transfers to optimize the bandwidth. This feature is only

available in FIFO mode

Incrementing or non-incrementing addressing for source and destination

Supports incremental burst transfers of 4, 8 or 16 beats. The size of the burst is

software-configurable, usually equal to half the FIFO size of the peripheral

Each stream supports circular buffer management

5 event flags (DMA half transfer, DMA transfer complete, DMA transfer error, DMA

FIFO error, direct mode error) logically ORed together in a single interrupt request for

DMA flow controller: the number of data items to be transferred is software-

programmable from 1 to 65535

Peripheral flow controller: the number of data items to be transferred is unknown

and controlled by the source or the destination peripheral that signals the end of

the transfer by hardware

RM0390 Rev 4

Chapters

Table of Contents

Do you have a question about the STM32F446 Series and is the answer not in the manual?