Status And Events Registers; Status Byte Register (Stb) - Pacific Power Source AFX Series Operation Manual

Command Syntax
Description
Parameters
Parameter Format
Example
Query Format
Description
Returned Data Format
Query Example
Query Format
Description
Returned Data Format
Query Example
Command Syntax
Description
Parameters
Parameter Format
Command Syntax
Description
Parameters
Parameter Format

8.12 Status and Events Registers

The IEEE488.2 standard defines a standardized status and events register system. Refer to
the ANSI/IEEE-488.2 1987 standard for more information. This section provides an overview
of these registers and bit positions for various status and error events.

8.12.1 Status Byte Register (STB)

The status register content is returned on a *STB? query. It contains 8 bits as shown in the
table below. The return value represents the 8 bits positions and can range from 0-255. A
*CLS command will clear the Status Byte Register (STB) and the Event Status Register (ESR).
Refer to Figure 8-2,"Status Byte Logical Model".
BIT NAME

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AFX Series Power Source Operation Manual
*SRE <nr1>
Before reading a status register, bits must be enabled. This command
enables bits in the service request register. The current setting is
saved in non-volatile memory.
0-255
<nr1>
*SRE 255
*SRE?
Reads the current state of the service request enable register. The
register is cleared after reading it. Refer to section 8.12 for register
bit values.
<nr1>
*SRE?
255
*STB?
Status Byte Query. The *STB? query returns the contents of the
status byte register (STB). After this query, the content of the STB
register is reset. Refer to section 8.12 for register bit values.
<nr1>
*STB?
4
*TRG
Triggers pending operation.
None
n/a
*WAI
Prohibits the instrument from executing any new commands until all
pending overlapped commands have been completed.
None
n/a
DEFINITION
AFX SERIES® OPERATION MANUAL
Remote Control Programming
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