Microchip Technology megaAVR 0 Series Manual page 393

26.5.5 LUT n Control A
Name: LUTCTRLA
Offset: 0x08 + n*0x04 [n=0..1]
Reset: 0x00
Property: Enable-Protected
Bit 7
EDGEDET
Access R/W
Reset 0
Bit 7 – EDGEDET Edge Detection
Value Description
0 Edge detector is disabled.
1 Edge detector is enabled.
Bit 6 – OUTEN Output Enable
This bit enables the LUT output to the LUTnOUT pin. When written to '1', the pin configuration of the
PORT I/O-Controller is overridden.
Value Description
0 Output to pin disabled.
1 Output to pin enabled.
Bits 5:4 – FILTSEL[1:0] Filter Selection
These bits select the LUT output filter options:
Filter Selection
Value Name
0x0 DISABLE
0x1 SYNCH
0x2 FILTER
0x3 -
Bits 3:1 – CLKSRC[2:0] Clock Source Selection
This bit selects between various clock sources to be used as the clock (CLK_MUX_OUT) for a LUT.
The CLK_MUX_OUT of the even LUT is used for clocking the Sequential block of a LUT pair.
Value Name
0x0 CLKPER
0x1 IN2
0x2 -
0x3 -
0x4 OSC20M
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2018 Microchip Technology Inc.
6 5
OUTEN FILTSEL[1:0]
R/W R/W
0 0
Description
None (masked)
LUT input 2
Reserved
Reserved
20MHz internal oscillator
CCL – Configurable Custom Logic
4 3
R/W R/W
0 0
Description
Filter disabled
Synchronizer enabled
Filter enabled
Reserved
Datasheet Preliminary
®
megaAVR
2 1
CLKSRC[2:0]
R/W R/W
0 0
DS40002015A-page 393
0-Series
0
ENABLE
R/W
0