Microchip Technology megaAVR 0 Series Manual page 309

22.5.8 Control C - Async Mode
Name: CTRLC
Offset: 0x07
Reset: 0x03
Property: -
This register description is valid for all modes except Master SPI mode. When the USART
Communication mode bits (CMODE) in this register are written to 'MSPI', see
Mode for the correct description.
Bit 7
CMODE[1:0]
Access
R/W
Reset 0
Bits 7:6 – CMODE[1:0] USART Communication Mode
Writing these bits select the Communication mode of the USART.
Writing a 0x3 to these bits alters the available bit fields in this register, see
Value Name
0x0 ASYNCHRONOUS
0x1 SYNCHRONOUS
0x2 IRCOM
0x3 MSPI
Bits 5:4 – PMODE[1:0] Parity Mode
Writing these bits enable and select the type of parity generation.
When enabled, the transmitter will automatically generate and send the parity of the transmitted data bits
within each frame. The receiver will generate a parity value for the incoming data, compare it to the
PMODE setting, and set the Parity Error flag (PERR) in the STATUS register (USARTn.STATUS) if a
mismatch is detected.
Value Name
0x0 DISABLED
0x1 -
0x2 EVEN
0x3 ODD
Bit 3 – SBMODE Stop Bit Mode
Writing this bit selects the number of Stop bits to be inserted by the transmitter.
The receiver ignores this setting.
Value Description
0 1 Stop bit
1 2 Stop bits
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2018 Microchip Technology Inc.
Universal Synchronous and Asynchronous Recei...
6 5
PMODE[1:0]
R/W R/W
0 0
4 3
SBMODE
R/W R/W
0 0
Description
Asynchronous USART
Synchronous USART
Infrared Communication
Master SPI
Description
Disabled
Reserved
Enabled, Even Parity
Enabled, Odd Parity
Datasheet Preliminary
®
megaAVR 0-Series
Control C - Master SPI
2 1
CHSIZE[2:0]
R/W R/W
0 1
Control C - Master SPI
DS40002015A-page 309
0
R/W
1
Mode.