Microchip Technology megaAVR 0 Series Manual page 478

Mnemonic Operands
SLEEP
WDR
Note:
1. Cycle time for data memory accesses assume internal RAM access and are not valid for accesses
to the NVM. A minimum of one extra cycle must be added when reading Flash and EEPROM.
2. One extra cycle must be added when accessing lower (64 bytes of) I/O space.
©
2018 Microchip Technology Inc.
Description Operation
Sleep (see also power
management and sleep
description)
Watchdog Reset (see also Watchdog
Controller description)
Datasheet Preliminary
®
megaAVR 0-Series
Instruction Set Summary
Flags #Clocks
None 1
None 1
DS40002015A-page 478