Microchip Technology megaAVR 0 Series Manual page 318

23.2.1 Block Diagram
Figure 23-1. SPI Block Diagram
MASTER
Transmit Data Register
(DATA)
Transmit Buffer
Register
MSb
8-bit Shift Register
First Receive Buffer
Register
Second Receive Buffer
Register
Receive Data Register
(DATA)
The SPI is built around an 8-bit Shift register that will shift data out and in at the same time. The Transmit
Data register and the Receive Data register are not physical registers but are mapped to other registers
when written or read: Writing the Transmit Data register (SPIn.DATA) will write the Shift register in Normal
mode and the Transmit Buffer register in Buffer mode. Reading the Receive Data register (SPIn.DATA)
will read the First Receive Buffer register in normal mode and the Second Receive Data register in Buffer
mode.
In Master mode, the SPI has a clock generator to generate the SCK clock. In Slave mode, the received
SCK clock is synchronized and sampled to trigger the shifting of data in the Shift register.
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2018 Microchip Technology Inc.
LSb
SPI CLOCK
GENERATOR
Serial Peripheral Interface (SPI)
MISO MISO
MOSI MOSI
SCK SCK
SS SS
Datasheet Preliminary
®
megaAVR 0-Series
SLAVE
Transmit Data Register
(DATA)
Transmit Buffer
Register
LSb
8-bit Shift Register
First Receive Buffer
Register
Receive Buffer
Register
Receive Data Register
(DATA)
DS40002015A-page 318
MSb