Serial Peripheral Interface (Spi); Features; Overview - Microchip Technology megaAVR 0 Series Manual

23.

Serial Peripheral Interface (SPI)

23.1

Features

• Full-Duplex, Three-Wire Synchronous Data Transfer
• Master or Slave Operation
• LSB First or MSB First Data Transfer
• Seven Programmable Bit Rates
• End of Transmission Interrupt Flag
• Write Collision Flag Protection
• Wake-up from Idle Mode
• Double-Speed (CK/2) Master SPI Mode
23.2

Overview

The Serial Peripheral Interface (SPI) is a high-speed synchronous data transfer interface using three or
four pins. It allows full duplex communication between an AVR device and peripheral devices or between
several microcontrollers. The SPI peripheral can be configured as either Master or Slave. The master
initiates and controls all data transactions.
The interconnection between master and slave devices with SPI is shown in the block diagram. The
system consists of two shift registers and a master clock generator. The SPI master initiates the
communication cycle by pulling the desired slave's slave select (SS) signal low. Master and slave prepare
the data to be sent to their respective shift registers, and the master generates the required clock pulses
on the SCK line to exchange data. Data is always shifted from master to slave on the master output,
slave input (MOSI) line, and from slave to master on the master input, slave output (MISO) line.
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2018 Microchip Technology Inc.
Serial Peripheral Interface (SPI)
Datasheet Preliminary
®
megaAVR 0-Series
DS40002015A-page 317