Microchip Technology megaAVR 0 Series Manual page 342

Figure 24-12. Bus State, State Diagram
After a system Reset and/or TWI master enable, the bus state is unknown. The bus state machine can be
forced to enter idle by writing to the Bus State bits accordingly. If no state is set by the application
software, the bus state will become idle when the first Stop condition is detected. If the master inactive
bus timeout is enabled, the bus state will change to idle on the occurrence of a timeout. After a known
bus state is established, only a system Reset or disabling of the TWI master will set the state to unknown.
When the bus is idle, it is ready for a new transaction. If a Start condition generated externally is
detected, the bus becomes busy until a Stop condition is detected. The Stop condition will change the
bus state to idle. If the master inactive bus timeout is enabled, the bus state will change from busy to idle
on the occurrence of a timeout.
If a Start condition is generated internally while in an Idle state, the owner state is entered. If the complete
transaction was performed without interference (i.e., no collisions are detected), the master will issue a
Stop condition and the bus state will change back to idle. If a collision is detected, the arbitration is
assumed lost and the bus state becomes busy until a Stop condition is detected. A repeated Start
condition will only change the bus state if arbitration is lost during the issuing of the repeated Start.
Arbitration during repeated Start can be lost only if the arbitration has been ongoing since the first Start
condition. This happens if two masters send the exact same ADDRESS+DATA before one of the masters'
issues a repeated Start (Sr).
24.3.4 Operation
24.3.4.1 Electrical Characteristics
The TWI module in AVR devices follows the electrical specifications and timing of I
These specifications are not 100% compliant, and so to ensure correct behavior, the inactive bus time-out
period should be set in TWI Master mode. Refer to
24.3.4.2 TWI Master Operation
The TWI master is byte-oriented, with an optional interrupt after each byte. There are separate interrupt
flags for master write and master read. Interrupt flags can also be used for polled operation. There are
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2018 Microchip Technology Inc.
RESET
UNKNOWN
(0b00)
P + Timeout
S
IDLE
P + Timeout
(0b01)
Command P
Write ADDRESS
OWNER
(S)
(0b10)
TWI Master Operation
Datasheet Preliminary
megaAVR
Two-Wire Interface (TWI)
Sr
BUSY
(0b11)
Arbitration
Lost
Write
ADDRESS(Sr)
for more details.
®
0-Series
2
C bus and SMBus.
DS40002015A-page 342