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Microchip Technology megaAVR 0 Series Manual page 48

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Table of Contents

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6.3.1
Register Summary - SYSCFG
Offset
Name
Bit Pos.
0x01
REVID
6.3.2
Register Description - SYSCFG
©
2018 Microchip Technology Inc.
7:0
REVID[7:0]
Datasheet Preliminary
®
megaAVR
0-Series
Peripherals and Architecture
DS40002015A-page 48
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