Microchip Technology megaAVR 0 Series Manual page 384

The edge detector is enabled by writing '1' to the Edge Selection bit (EDGEDET) in the LUT n Control A
register (CCL.LUTnCTRLA). In order to avoid unpredictable behavior, a valid filter option must be enabled
as well.
Edge detection is disabled by writing a '0' to EDGEDET in CCL.LUTnCTRLA. After disabling an LUT, the
corresponding internal Edge Detector logic is cleared one clock cycle later.
Figure 26-6. Edge Detector
26.3.2.6 Sequential Logic
Each LUT pair can be connected to an internal Sequential block. A Sequential block can function as
either D flip-flop, JK flip-flop, gated D-latch, or RS-latch. The function is selected by writing the Sequential
Selection bits (SEQSEL) in the Sequential Control register (SEQCTRLn).
The Sequential block receives its input from the either LUT, filter, or edge detector, depending on the
configuration.
The Sequential block is clocked by the same clock as the corresponding LUT. The clock source is
selected by the Clock Source field (CLKSRC) in the LUT n Control A register (LUTnCTRLA).
When the even LUT (LUT2n) is disabled, the latch is asynchronously cleared, during which the flip-flop
reset signal (R) is kept enabled for one clock cycle. In all other cases, the flip-flop output (OUT) is
refreshed on the rising edge of the clock, as shown in the respective "Electrical Characteristics" section in
the device Data Sheet.
Gated D Flip-Flop (DFF)
The D-input is driven by the even LUT output (LUT2n), and the G-input is driven by the odd LUT output
(LUT2n+1).
Figure 26-7. D Flip-Flop
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2018 Microchip Technology Inc.
CLK_MUX_OUT
even LUT
CLK_MUX_OUT
odd LUT
CCL – Configurable Custom Logic
Datasheet Preliminary
®
megaAVR 0-Series
DS40002015A-page 384