Microchip Technology megaAVR 0 Series Manual page 343

dedicated status flags for indicating ACK/NACK received, bus error, arbitration lost, clock hold, and bus
state.
When an interrupt flag is set, the SCL line is forced low. This will give the master time to respond or
handle any data, and will in most cases require software interaction.
operation. The diamond-shaped symbols (SW) indicate where software interaction is required. Clearing
the interrupt flags releases the SCL line.
Figure 24-13. TWI Master Operation
APPLICATION
M1 M2
BUSY P IDLE
Wait for
SW
IDLE
SW Driver software
The master provides data
on the bus
Slave provides data on
the bus
Bus state
Mn
Diagram connections
The number of interrupts generated is kept to a minimum by an automatic handling of most conditions.
Clock Generation
The TWIn.MBAUD register must be set to a value that results in a TWI bus clock frequency (f
or less than 100 kHz/400 kHz/1 MHz, dependent on the mode used by the application (Standard mode
Sm/Fast mode Fm/Fast mode plus Fm+).
The low (T ) and high (T
LOW
the rise (T ) and fall (T
RISE
of the bus, T will be considered as part of T
FALL
T until a high state has been detected.
HIGH
©
2018 Microchip Technology Inc.
M3
S ADDRESS
) times are determined by the Baud Rate register (TWIn.MBAUD), while
HIGH
) times are determined by the bus topology. Because of the wired-AND logic
FALL
LOW
Datasheet Preliminary
megaAVR
Two-Wire Interface (TWI)
Figure 24-13
MASTER WRITE INTERRUPT + HOLD
M4
R/W BUSY BUSY
SW
R/W A P
SW
W A SW Sr
SW
MASTER READ INTERRUPT + HOLD
A BUSY
SW
A/A P
A/A Sr
A/A
R A
. Likewise, T will be in a state between T
RISE
®
0-Series
shows the TWI master
M1
M2
IDLE
M3
BUSY
DATA A/A
M4
M2
IDLE
M3
DATA
) equal
SCL
and
LOW
DS40002015A-page 343
M4