Functional Description - Microchip Technology megaAVR 0 Series Manual

12.2.1 Block Diagram
Figure 12-1. CPUINT Block Diagram
Peripheral 1
INT LEVEL
Peripheral n
INT REQ
INT ACK
12.3

Functional Description

12.3.1 Initialization
An interrupt must be initialized in the following order:
1. Configure the CPUINT if the default configuration is not adequate (optional):
– Vector handling is configured by writing to the respective bits (IVSEL and CVT) in the Control
A register (CPUINT.CTRLA).
– Vector prioritizing by round robin is enabled by writing a '1' to the Round Robin Priority Enable
bit (LVL0RR) in CPUINT.CTRLA.
– Select the priority level 1 vector by writing its address to the Interrupt Vector (LVL1VEC) in the
Level 1 Priority register (CPUINT.LVL1VEC).
2. Configure the interrupt conditions within the peripheral, and enable the peripheral's interrupt.
3. Enable interrupts globally by writing a '1' to the Global Interrupt Enable bit (I) in the CPU Status
register (CPU.SREG).
12.3.2 Operation
12.3.2.1 Enabling, Disabling, and Resetting
Global enabling of interrupts is done by writing a '1' to the Global Interrupt Enable bit (I) in the CPU Status
register (CPU.SREG). To disable interrupts globally, write a '0' to the I bit in CPU.SREG.
The desired interrupt lines must also be enabled in the respective peripheral, by writing to the peripheral's
Interrupt Control register (peripheral.INTCTRL).
Interrupt flags are not automatically cleared after the interrupt is executed. The respective INTFLAGS
register descriptions provide information on how to clear specific flags.
12.3.2.2 Interrupt Vector Locations
The Interrupt vector placement is dependent on the value of Interrupt Vector Select bit (IVSEL) in the
Control A register (CPUINT.CTRLA). Refer to the IVSEL description in CPUINT.CTRLA for the possible
locations.
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2018 Microchip Technology Inc.
Interrupt Controller
INT REQ
INT REQ
CPU Interrupt Controller (CPUINT)
Priority
Decoder
Global
STATUS
Interrupt
Enable
LVL0PRI
LVL1VEC
CPU.SREG
Datasheet Preliminary
®
megaAVR 0-Series
CPU "RETI"
CPU INT ACK
CPU
CPU INT REQ
Sleep
Wake-up
Controller
DS40002015A-page 106