Microchip Technology megaAVR 0 Series Manual page 64

BOOTEND APPEND
> 0 ==
BOOTEND
> 0 >
BOOTEND
Note:
• See also the BOOTEND and APPEND descriptions.
• Interrupt vectors are by default located after the BOOT section. This can be changed in the
interrupt controller.
If FUSE.BOOTEND is written to 0x04 and FUSE.APPEND is written to 0x08, the first
4*256 bytes will be BOOT, the next 4*256 bytes will be APPCODE, and the remaining
Flash will be APPDATA.
Inter-Section Write Protection
Between the three Flash sections, a directional write protection is implemented:
• Code in the BOOT section can write to APPCODE and APPDATA
• Code in APPCODE can write to APPDATA
• Code in APPDATA cannot write to Flash or EEPROM
Boot Section Lock and Application Code Section Write Protection
The two lockbits (APCWP and BOOTLOCK in NVMCTRL.CTRLB) can be set to lock further updates of
the respective APPCODE or BOOT section until the next Reset.
The CPU can never write to the BOOT section. NVMCTRL_CTRLB.BOOTLOCK prevents reads and
execution of code from the BOOT section.
8.3.1.2 EEPROM
The EEPROM is divided into a set of pages where one page consists of multiple bytes. The EEPROM
has byte granularity on erase/write. Within one page only the bytes marked to be updated will be erased/
written. The byte is marked by writing a new value to the page buffer for that address location.
8.3.1.3 User Row
The User Row is one extra page of EEPROM. This page can be used to store various data, such as
calibration/configuration data and serial numbers. This page is not erased by a chip erase. The User Row
is written as normal EEPROM, but in addition, it can be written through UPDI on a locked device.
8.3.2 Memory Access
8.3.2.1 Read
Reading of the Flash and EEPROM is done by using load instructions with an address according to the
memory map. Reading any of the arrays while a write or erase is in progress will result in a bus wait, and
the instruction will be suspended until the ongoing operation is complete.
8.3.2.2 Page Buffer Load
The page buffer is loaded by writing directly to the memories as defined in the memory map. Flash,
EEPROM, and User Row share the same page buffer so only one section can be programmed at a time.
The Least Significant bits (LSb) of the address are used to select where in the page buffer the data is
©
2018 Microchip Technology Inc.
Nonvolatile Memory Controller (NVMCTRL)
BOOT Section
0 to 256*BOOTEND
0 to 256*BOOTEND
Datasheet Preliminary
megaAVR
APPCODE Section
-
256*BOOTEND to
256*APPEND
®
0-Series
APPDATA Section
256*BOOTEND to
FLASHEND
256*APPEND to
FLASHEND
DS40002015A-page 64