Microchip Technology megaAVR 0 Series Manual page 55

Figure 7-5. The X-, Y-, and Z-Registers
Bit (individually)
X-register
Bit (X-register)
Bit (individually)
Y-register
Bit (Y-register)
Bit (individually)
Z-register
Bit (Z-register)
The lowest register address holds the Least Significant Byte (LSB), and the highest register address
holds the Most Significant Byte (MSB). In the different addressing modes, these address registers
function as fixed displacement, automatic increment, and automatic decrement.
7.5.6 Accessing 16-Bit Registers
The AVR data bus has a width of 8 bit, and so accessing 16-bit registers requires atomic operations.
These registers must be byte accessed using two read or write operations. 16-bit registers are connected
to the 8-bit bus and a temporary register using a 16-bit bus.
For a write operation, the low byte of the 16-bit register must be written before the high byte. The low byte
is then written into the temporary register. When the high byte of the 16-bit register is written, the
temporary register is copied into the low byte of the 16-bit register in the same clock cycle.
For a read operation, the low byte of the 16-bit register must be read before the high byte. When the low
byte register is read by the CPU, the high byte of the 16-bit register is copied into the temporary register
in the same clock cycle as the low byte is read. When the high byte is read, it is then read from the
temporary register.
This ensures that the low and high bytes of 16-bit registers are always accessed simultaneously when
reading or writing the register.
Interrupts can corrupt the timed sequence if an interrupt is triggered and accesses the same 16-bit
register during an atomic 16-bit read/write operation. To prevent this, interrupts can be disabled when
writing or reading 16-bit registers.
The temporary registers can be read and written directly from user software.
7.5.7 Configuration Change Protection (CCP)
System critical I/O register settings are protected from accidental modification. Flash self-programming
(via store to NVM controller) is protected from accidental execution. This is handled globally by the
Configuration Change Protection (CCP) register.
Changes to the protected I/O registers or bits, or execution of protected instructions, are only possible
after the CPU writes a signature to the CCP register. The different signatures are listed in the description
of the CCP register (CPU.CCP).
There are two modes of operation: one for protected I/O registers, and one for the protected self-
programming.
7.5.7.1 Sequence for Write Operation to Configuration Change Protected I/O Registers
In order to write to registers protected by CCP, these steps are required:
©
2018 Microchip Technology Inc.
7 R27
XH
15
7 R29
YH
15
7 R31
ZH
15
Datasheet Preliminary
megaAVR
0 7 R26
XL
8 7
0 7 R28
YL
8
7
0 7 R30
ZL
8 7
®
0-Series
AVR CPU
0
0
0
0
0
0
DS40002015A-page 55