Register Summary - Tcan In Split Mode (Splitm In Tcan.ctrld=1); Register Description - Split Mode - Microchip Technology megaAVR 0 Series Manual

19.7

Register Summary - TCAn in Split Mode (SPLITM in TCAn.CTRLD=1)

Offset Name Bit Pos.
0x00 CTRLA
0x01 CTRLB
0x02 CTRLC
0x03 CTRLD
0x04 CTRLECLR
0x05 CTRLESET
0x06
... Reserved
0x09
0x0A INTCTRL
0x0B INTFLAGS
0x0C
... Reserved
0x0D
0x0E DBGCTRL
0x0F
... Reserved
0x1F
0x20 LCNT
0x21 HCNT
0x22
... Reserved
0x25
0x26 LPER
0x27 HPER
0x28 LCMP0
0x29 HCMP0
0x2A LCMP1
0x2B HCMP1
0x2C LCMP2
0x2D HCMP2
19.8

Register Description - Split Mode

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2018 Microchip Technology Inc.
7:0
7:0 HCMP2EN
7:0 HCMP2OV
7:0
7:0
7:0
7:0 LCMP2
7:0 LCMP2
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
16-bit Timer/Counter Type A (TCA)
HCMP1EN HCMP0EN
HCMP1OV HCMP0OV
LCMP1 LCMP0
LCMP1 LCMP0
LCNT[7:0]
HCNT[7:0]
LPER[7:0]
HPER[7:0]
LCMP[7:0]
HCMP[7:0]
LCMP[7:0]
HCMP[7:0]
LCMP[7:0]
HCMP[7:0]
Datasheet Preliminary
®
megaAVR 0-Series
CLKSEL[2:0]
LCMP2EN LCMP1EN
LCMP2OV LCMP1OV
CMD[1:0] CMDEN[1:0]
CMD[1:0] CMDEN[1:0]
HUNF
HUNF
DS40002015A-page 218
ENABLE
LCMP0EN
LCMP0OV
SPLITM
LUNF
LUNF
DBGRUN