Cyclic Redundancy Check Memory Scan (Crcscan); Features; Overview - Microchip Technology megaAVR 0 Series Manual

25.

Cyclic Redundancy Check Memory Scan (CRCSCAN)

25.1

Features

• CRC-16-CCITT
• Check of the entire Flash section, application code, and/or boot section
• Selectable NMI trigger on failure
• User configurable check during internal reset initialization
25.2

Overview

A Cyclic Redundancy Check (CRC) takes a data stream of bytes from the NVM (either the entire Flash,
only the Boot section, or both application code and Boot section) and generates a checksum. The CRC
peripheral (CRCSCAN) can be used to detect errors in the program memory:
The last location in the section to check has to contain the correct pre-calculated 16-bit checksum for
comparison. If the checksum calculated by the CRCSCAN and the pre-calculated checksums match, a
status bit in the CRCSCAN is set. If they do not match, the status register will indicate that it failed. The
user can choose to let the CRCSCAN generate a non-maskable interrupt (NMI) if the checksums do not
match.
An n-bit CRC, applied to a data block of arbitrary length, will detect any single alteration (error burst) up to
n bits in length. For longer error bursts, a fraction 1-2
The CRC-generator supports CRC-16-CCITT.
Polynomial:
• CRC-16-CCITT: x
The CRC reads in byte-by-byte of the content of the section(s) it is set up to check, starting with byte 0,
and generates a new checksum per byte. The byte is sent through a shift register as depicted below,
starting with the most significant bit. If the last bytes in the section contain the correct checksum, the CRC
will pass. See Checksum
0xFFFF.
Figure 25-1. CRC Implementation Description
data
15
x
Q D
©
2018 Microchip Technology Inc.
Cyclic Redundancy Check Memory Scan (CRCSCAN...
16 12 5
+ x + x + 1
for how to place the checksum. The initial value of the checksum register is
14 13 12 11
x x x x
Q D Q D Q D Q D
-n
will be detected.
10 9 8 7 6
x x x x x
Q D Q D Q D Q D Q D
Datasheet Preliminary
®
megaAVR
5 4 3 2
x x x x
Q D Q D Q D Q D
DS40002015A-page 370
0-Series
1 0
x x
Q D Q D