Microchip Technology megaAVR 0 Series Manual page 200

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19.6.2
Control B - Normal Mode
Name: 
CTRLB
Offset: 
0x01
Reset: 
0x00
Property:  -
Bit
7
Access
Reset
Bits 4, 5, 6 – CMPEN Compare n Enable
In the FRQ or PWM Waveform Generation mode, these bits will override the PORT output register for the
corresponding pin.
Value
Description
0
Port output settings for the pin with WOn output respected
1
Port output settings for pin with WOn output overridden in FRQ or PWM Waveform
Generation mode
Bit 3 – ALUPD Auto-Lock Update
The Auto-Lock Update feature controls the Lock Update (LUPD) bit in the TCAn.CTRLE register. When
ALUPD is written to '1', LUPD will be set to '1' until the Buffer Valid (CMPnBV) bits of all enabled compare
channels are '1'. This condition will clear LUPD.
It will remain cleared until the next UPDATE condition, where the buffer values will be transferred to the
CMPn registers and LUPD will be set to '1' again. This makes sure that CMPnBUF register values are not
transferred to the CMPn registers until all enabled compare buffers are written.
Value
Description
0
LUPD in TCA.CTRLE not altered by system
1
LUPD in TCA.CTRLE set and cleared automatically
Bits 2:0 – WGMODE[2:0] Waveform Generation Mode
These bits select the Waveform Generation mode and control the counting sequence of the counter, TOP
value, UPDATE condition, interrupt condition, and type of waveform that is generated.
No waveform generation is performed in the Normal mode of operation. For all other modes, the result
from the waveform generator will only be directed to the port pins if the corresponding CMPnEN bit has
been set to enable this. The port pin direction must be set as output.
Table 19-4. Timer Waveform Generation Mode
WGMODE[2:0] Group Configuration Mode of Operation Top
000
001
010
011
©
2018 Microchip Technology Inc.
6
5
CMP2EN
CMP1EN
R/W
R/W
0
0
NORMAL
FRQ
-
SINGLESLOPE
16-bit Timer/Counter Type A (TCA)
4
3
CMP0EN
ALUPD
R/W
R/W
0
0
Normal
PER
Frequency
CMP0 TOP
Reserved
-
Single-slope PWM
PER
Datasheet Preliminary
®
megaAVR
0-Series
2
1
WGMODE[2:0]
R/W
R/W
0
0
Update
OVF
TOP
TOP
TOP
-
-
BOTTOM BOTTOM
DS40002015A-page 200
0
R/W
0

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