Microchip Technology megaAVR 0 Series Manual page 178

18.3.3.3 Configuration Protection and Lock
The WDT provides two security mechanisms to avoid unintentional changes to the WDT settings:
The first mechanism is the Configuration Change Protection mechanism, employing a timed write
procedure for changing the WDT control registers.
The second mechanism locks the configuration by writing a '1' to the LOCK bit in the STATUS register
(WDT.STATUS). When this bit is '1', the Control A register (WDT.CTRLA) cannot be changed.
Consequently, the WDT cannot be disabled from software.
LOCK in WDT.STATUS can only be written to '1'. It can only be cleared in Debug mode.
If the WDT configuration is loaded from fuses, LOCK is automatically set in WDT.STATUS.
18.3.4 Sleep Mode Operation
The WDT will continue to operate in any sleep mode where the source clock is active.
18.3.5 Debug Operation
When run-time debugging, this peripheral will continue normal operation. Halting the CPU in Debugging
mode will halt normal operation of the peripheral.
When halting the CPU in Debug mode, the WDT counter is reset.
When starting the CPU again and the WDT is operating in Window mode, the first closed window time-
out period will be disabled, and a Normal mode time-out period is executed.
18.3.6 Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domain, the Control A
register (WDT.CTRLA) is synchronized when written. The Synchronization Busy flag (SYNCBUSY) in the
STATUS register (WDT.STATUS) indicates if there is an ongoing synchronization.
Writing to WDT.CTRLA while SYNCBUSY=1 is not allowed.
The following registers are synchronized when written:
• PERIOD bits in Control A register (WDT.CTRLA)
• Window Period bits (WINDOW) in WDT.CTRLA
The WDR instruction will need two to three cycles of the WDT clock in order to be synchronized. Issuing a
new WDR instruction while a WDR instruction is being synchronized will be ignored.
18.3.7 Configuration Change Protection
This peripheral has registers that are under Configuration Change Protection (CCP). In order to write to
these, a certain key must be written to the CPU.CCP register first, followed by a write access to the
protected bits within four CPU instructions.
It is possible to try writing to these registers at any time, but the values are not altered.
The following registers are under CCP:
Table 18-1. WDT - Registers Under Configuration Change Protection
Register
WDT.CTRLA
LOCK bit in WDT.STATUS
List of bits/registers protected by CCP:
©
2018 Microchip Technology Inc.
Datasheet Preliminary
®
megaAVR 0-Series
Watchdog Timer (WDT)
Key
IOREG
IOREG
DS40002015A-page 178