Microchip Technology megaAVR 0 Series Manual page 322

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megaAVR 0-Series
Serial Peripheral Interface (SPI)
Note:
In Slave mode, the SPI state machine will be reset when the SS pin is brought high. If the SS is brought
high during a transmission, the SPI will stop sending and receiving immediately and both data received
and data sent must be considered as lost. As the SS pin is used to signal the start and end of a transfer, it
is useful for achieving packet/byte synchronization, and keeping the Slave bit counter synchronized with
the master clock generator.
Normal Mode
In Normal mode, the SPI peripheral will remain idle as long as the SS pin is driven high. In this state, the
software may update the contents of the SPIn.DATA register, but the data will not be shifted out by
incoming clock pulses on the SCK pin until the SS pin is driven low. If SS is driven low, the slave will start
to shift out data on the first SCK clock pulse. When one byte has been completely shifted, the SPI
Interrupt flag (IF) in SPIn.INTFLAGS is set.
The user application may continue placing new data to be sent into the SPIn.DATA register before
reading the incoming data. New bytes to be sent cannot be written to SPIn.DATA before the entire
transfer has completed. A premature write will be ignored, and the hardware will set the Write Collision
Flag (WRCOL in SPIn.INTFLAGS).
When SS is driven high, the SPI logic is halted, and the SPI slave will not receive any new data. Any
partially received packet in the shift register will be lost.
Figure 23-2. SPI Timing Diagram in Normal Mode (Buffer Mode Not Enabled)
SS
SCK
Write DATA
Write value 0x46
0x43 0x44 0x45
WRCOL
IF
Shift Register
0x43 0x46
0x44
Data sent
0x43 0x44
0x46
The figure shows three transfers and one write to the DATA register while the SPI is busy with a transfer.
This write will be ignored and the Write Collision Flag (WRCOL in SPIn.INTFLAGS) is set.
Buffer Mode
To avoid data collisions, the SPI peripheral can be configured in buffered mode by writing a '1' to the
Buffer Mode Enable bit in the Control B register (BUFEN in SPIn.CTRLB). In this mode, the SPI has
additional interrupt flags and extra buffers. The extra buffers are shown in Figure 23-1. There are two
different modes for the Buffer mode, selected with the Buffer mode Wait for Receive bit (BUFWR). The
two different modes are described below with timing diagrams.
Datasheet Preliminary
DS40002015A-page 322
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