Functional Description - Microchip Technology megaAVR 0 Series Manual

Figure 29-2. UPDI Clock Domains
Controller
UPDI clk
29.2.3 Power Management
The UPDI physical layer continues to operate in any Sleep mode and is always accessible for a
connected debugger, but read/write access to the system bus is restricted in Sleep modes where the
CPU clock is switched off. The UPDI can be enabled at any time, independent of the system Sleep state.
See Sleep Mode Operation
29.3

Functional Description

29.3.1 Principle of Operation
Communication through the UPDI is based on standard UART communication, using a fixed frame
format, and automatic baud rate detection for clock and data recovery. In addition to the data frame, there
are several control frames which are important to the communication. The supported frame formats are
presented in Figure
©
2018 Microchip Technology Inc.
ASI
UPDI Controller
UPDI
Physical
layer
Clock
Clk_UPDI
source
UPDI
~
CLKSEL
for details on UPDI operation during Sleep modes.
29-3.
Unified Program and Debug Interface (UPDI)
UPDI
Access
layer
Datasheet Preliminary
®
megaAVR 0-Series
Clock
Controller
Clk_sys
Clk_sys
~
DS40002015A-page 441