Microchip Technology megaAVR 0 Series Manual page 282

22.2.1 Block Diagram
Figure 22-1. USART Block Diagram
22.2.2 Signal Description
Signal
RxD
TxD
XCK
XDIR
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2018 Microchip Technology Inc.
Universal Synchronous and Asynchronous Recei...
BAUD
Fractional Baud Rate
Generator
TXDATA
Transmit Shift Register
Receive Shift Register
RXDATA Buffer
RXDATA
Type
Input/output
Output
Input/output
Output
OSC
Sync Logic
Parity
Generator
Clock
Recovery
Data
Recovery
Parity
Checker
Description
Receiving line
Transmitting line
Clock for synchronous operation
Transmit Enable for RS485
Datasheet Preliminary
®
megaAVR
Clock Generator
Pin
Control
Transmitter
TX
Control
Pin
Control
Receiver
RX
Control
Pin
Control
DS40002015A-page 282
0-Series
XCK
XDIR
TxD
RxD