Microchip Technology megaAVR 0 Series Manual page 286

Table 22-2. Functionality of INVEN in PORTx.PINnCTRL and UCPHA in USARTn.CTRLC
SPI Mode
0
1
2
3
The leading edge is the first clock edge of a clock cycle. The trailing edge is the last clock edge of a clock
cycle.
Figure 22-4. UCPHA and INVEN Data Transfer Timing Diagrams
SPI Mode 1
XCK
Data setup (TXD)
Data sample (RXD)
SPI Mode 0
XCK
Data setup (TXD)
Data sample (RXD)
22.3.2.2 Frame Formats
Data transfer is frame based, where a serial frame consists of one character of data bits with
synchronization bits (Start and Stop bits) and an optional parity bit for error checking. This does not apply
to master SPI operation (see
as valid frame formats:
• 1 Start bit
• 5, 6, 7, 8, or 9 Data bits
• No, even, or odd Parity bit
• 1 or 2 Stop bits
Figure 22-5 illustrates the possible combinations of frame formats. Bits inside brackets are optional.
Figure 22-5. Frame Formats
©
2018 Microchip Technology Inc.
Universal Synchronous and Asynchronous Recei...
INVEN UCPHA
0 0
0 1
1 0
1 1
INVEN=0
SPI Frame Formats.) The USART accepts all combinations of the following
Datasheet Preliminary
megaAVR
Leading Edge
Rising, sample
Rising, setup
Falling, sample
Falling, setup
SPI Mode 3
XCK
Data setup (TXD)
Data sample (RXD)
SPI Mode 2
XCK
Data setup (TXD)
Data sample (RXD)
®
0-Series
Trailing Edge
Falling, setup
Falling, sample
Rising, setup
Rising, sample
INVEN=1
DS40002015A-page 286