Avr Cpu; Features; Overview; Architecture - Microchip Technology megaAVR 0 Series Manual

7.

AVR CPU

7.1

Features

• 8-bit, high-performance AVR RISC CPU
– 135 instructions
– Hardware multiplier
• 32 8-bit registers directly connected to the ALU
• Stack in RAM
• Stack pointer accessible in I/O memory space
• Direct addressing of up to 64 KB of unified memory
• Efficient support for 8-, 16-, and 32-bit arithmetic
• Configuration Change Protection for system-critical features
• Native OCD support
– Two hardware breakpoints
– Change of flow, interrupt and software breakpoints
– Run-time readout of Stack Pointer register, program counter (PC), and Status register
– Register file read- and writable in stopped mode
7.2

Overview

All AVR devices use the 8-bit AVR CPU. The CPU is able to access memories, perform calculations,
control peripherals, and execute instructions in the program memory. Interrupt handling is described in a
separate section.
7.3

Architecture

In order to maximize performance and parallelism, the AVR CPU uses a Harvard architecture with
separate buses for program and data. Instructions in the program memory are executed with single-level
pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program
memory. This enables instructions to be executed on every clock cycle.
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2018 Microchip Technology Inc.
Datasheet Preliminary
®
megaAVR 0-Series
AVR CPU
DS40002015A-page 50