Microchip Technology megaAVR 0 Series Manual page 354

24.5.5 Master Control B
Name: MCTRLB
Offset: 0x04
Reset: 0x00
Property: -
Bit 7
Access
Reset
Bit 3 – FLUSH Flush
Writing a '1' to this bit generates a strobe for one clock cycle disabling and then enabling the master.
Writing '0' has no effect.
The purpose is to clear the internal state of master: For TWI master to transmit successfully, it is
recommended to write the Master Address register (TWIn.MADDR) first and then the Master Data
register (TWIn.MDATA).
The peripheral will transmit invalid data if TWIn.MDATA is written before TWIn.MADDR. To avoid this
invalid transmission, write '1' to this bit to clear both registers.
Bit 2 – ACKACT Acknowledge Action
This bit defines the master's behavior under certain conditions defined by the bus protocol state and
software interaction. The acknowledge action is performed when DATA is read, or when an execute
command is written to the CMD bits.
The ACKACT bit is not a flag or strobe, but an ordinary read/write accessible register bit. The default
ACKACT for master read interrupt is "Send ACK" (0). For master write, the code will know that no
acknowledge should be sent since it is itself sending data.
Value Description
0 Send ACK
1 Send NACK
Bits 1:0 – MCMD[1:0] Command
The master command bits are strobes. These bits are always read as zero.
Writing to these bits triggers a master operation as defined by the table below.
Table 24-4. Command Settings
MCMD[1:0] DIR Description
0x0 X
0x1 X
0x2 0
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2018 Microchip Technology Inc.
6 5
NOACT - No action
REPSTART - Execute Acknowledge Action succeeded by repeated Start.
RECVTRANS - Execute Acknowledge Action succeeded by a byte read operation.
4 3
FLUSH ACKACT
R/W
0
Datasheet Preliminary
®
megaAVR 0-Series
Two-Wire Interface (TWI)
2 1
MCMD[1:0]
R/W R/W
0 0
DS40002015A-page 354
0
R/W
0