Microchip Technology megaAVR 0 Series Manual page 78

9.2.1 Block Diagram - CLKCTRL
Figure 9-1. CLKCTRL Block Diagram
NVM
Main Clock Prescaler
Main Clock Switch
OSCULP32K
OSC20M
OSC20M
int. Oscillator
The clock system consists of the main clock and other asynchronous clocks:
• Main Clock
This clock is used by the CPU, RAM, Flash, the I/O bus, and all peripherals connected to the I/O
bus. It is always running in Active and Idle Sleep mode and can be running in Standby Sleep mode
if requested.
The main clock CLK_MAIN is prescaled and distributed by the clock controller:
• CLK_CPU is used by the CPU, SRAM, and the NVMCTRL peripheral to access the
nonvolatile memory
• CLK_PER is used by all peripherals that are not listed under asynchronous clocks.
• Clocks running asynchronously to the main clock domain:
– CLK_RTC is used by the RTC/PIT. It will be requested when the RTC/PIT is enabled. The
clock source for CLK_RTC should only be changed if the peripheral is disabled.
– CLK_WDT is used by the WDT. It will be requested when the WDT is enabled.
©
2018 Microchip Technology Inc.
RAM CPU
CLKOUT
CLK_CPU
CLK_PER
CLK_MAIN
XOSC32K
32 KHz ULP
Int. Oscillator ext. Crystal Osc.
RTC
Other
INT
Peripherals
PRESCALER
CLK_RTC
RTC
CLKSEL
XOSC32K
SEL
32.768 kHz
EXTCLK
TOSC2 TOSC1
Datasheet Preliminary
®
megaAVR 0-Series
Clock Controller (CLKCTRL)
WDT
BOD
CLK_WDT CLK_BOD CLK_TCD
DS40002015A-page 78
TCD
TCD
CLKCSEL