Functional Description - Microchip Technology megaAVR 0 Series Manual

23.2.2 Signal Description
Table 23-1. Signals in Master and Slave Mode
Signal
MOSI
MISO
SCK
SS
When the SPI module is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden
according to Table
The data direction of the pins with "User defined" pin configuration is not controlled by the SPI: The data
direction is controlled by the application software configuring the port peripheral. If these pins are
configured with data direction as input, they can be used as regular I/O pin inputs. If these pins are
configured with data direction as output, their output value is controlled by the SPI. The MISO pin has a
special behavior: When the SPI is in Slave mode and the MISO pin is configured as an output, the SS pin
controls the output buffer of the pin: If SS is low, the output buffer drives the pin, if SS is high, the pin is
tri-stated.
The data direction of the pins with "Input" pin configuration is controlled by the SPI hardware.
23.3

Functional Description

23.3.1 Initialization
Initialize the SPI to a basic functional state by following these steps:
1. Configure the SS pin in the port peripheral.
2. Select SPI Master/Slave operation by writing the Master/Slave Select bit (MASTER) in the Control
A register (SPIn.CTRLA).
3. In Master mode, select the clock speed by writing the Prescaler bits (PRESC) and the Clock
Double bit (CLK2X) in SPIn.CTRLA.
4. Optional: Select the Data Transfer mode by writing to the MODE bits in the Control B register
(SPIn.CTRLB).
5. Optional: Write the Data Order bit (DORD) in SPIn.CTRLA.
6. Optional: Setup Buffer mode by writing BUFEN and BUFWR bits in the Control B register
(SPIn.CTRLB).
7. Optional: To disable the multi-master support in Master mode, write '1' to the Slave Select Disable
bit (SSD) in SPIn.CTRLB.
8. Enable the SPI by writing a '1' to the ENABLE bit in SPIn.CTRLA.
23.3.2 Operation
23.3.2.1 Master Mode Operation
When the SPI is configured in Master mode, a write to the SPIn.DATA register will start a new transfer.
The SPI clock generator starts and the hardware shifts the eight bits into the selected slave. After the
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2018 Microchip Technology Inc.
Description
Master Out Slave In
Master In Slave Out
Slave clock
Slave select
23-1.
Serial Peripheral Interface (SPI)
Pin Configuration
Master Mode
User defined
Input
User defined
User defined
Datasheet Preliminary
®
megaAVR 0-Series
Slave Mode
Input
User defined
Input
Input
DS40002015A-page 319