Microchip Technology megaAVR 0 Series Manual page 365

24.5.12 Slave Status
Name: SSTATUS
Offset: 0x0B
Reset: 0x00
Property: -
Normal TWI operation dictates that the Slave Status register should be regarded purely as a read-only
register. Clearing any of the status flags will indirectly be done when accessing the Slave Data
(TWIn.SDATA) register or the CMD bits in the Slave Control B register (TWIn.SCTRLB).
Bit 7
DIF
Access
R/W
Reset 0
Bit 7 – DIF Data Interrupt Flag
This flag is set when a slave byte transmit or byte receive operation is successfully completed without any
bus error. The flag can be set with an unsuccessful transaction in case of collision detection (see the
description of the COLL Status bit). Writing a '1' to its bit location will clear the DIF. However, normal use
of the TWI does not require the DIF flag to be cleared by using this method, since the flag is automatically
cleared when:
1. Writing to the Slave DATA register.
2. Reading the Slave DATA register.
3. Writing a valid command to the CTRLB register.
The DIF flag can be used to generate a slave data interrupt (see the description of the DIEN control bit in
TWIn.CTRLA).
Bit 6 – APIF Address or Stop Interrupt Flag
This flag is set when the slave address match logic detects that a valid address has been received or by
a Stop condition. Writing a '1' to its bit location will clear the APIF. However, normal use of the TWI does
not require the flag to be cleared by this method since the flag is cleared using the same software
interactions as described for the DIF flag.
The APIF flag can be used to generate a slave address or stop interrupt (see the description of the AIEN
control bit in TWIn.CTRLA). Take special note of that the slave stop interrupt shares the interrupt vector
with the slave address interrupt.
Bit 5 – CLKHOLD Clock Hold
If read as '1', the slave clock hold flag indicates that the slave is currently holding the TWI clock (SCL)
low, stretching the TWI clock period. This is a read-only bit that is set when an address or data interrupt is
set. Resetting the corresponding interrupt will indirectly reset this flag.
Bit 4 – RXACK Received Acknowledge
This bit is read-only and contains the most recently received Acknowledge bit from the master. When
read as zero, the most recent acknowledge bit from the master was ACK. When read as one, the most
recent acknowledge bit was NACK.
©
2018 Microchip Technology Inc.
6 5
APIF CLKHOLD
R/W R
0 0
4 3
RXACK COLL
R R/W
0 0
Datasheet Preliminary
®
megaAVR 0-Series
Two-Wire Interface (TWI)
2 1
BUSERR DIR
R/W R
0 0
DS40002015A-page 365
0
AP
R
0