Microchip Technology ZL30641 Quick Start Manual

5 Channels, 10 Inputs, 20 Outputs Product Brief
Features
Highlights
• Up to five independent clock channels
• Any-to-any frequency conversion per channel
• Inputs: up to 10, differential or single-ended
• Outputs: up to 10 differential, up to 20 CMOS
• Output jitter 100 fs typical for 156.25 MHz
RMS
12 kHz to 20 MHz
• Core power consumption <0.9W
TM
• MiToDSync 1-wire time-of-day interface in/out
TM
• MiToDBasic 3-wire time-of-day interface out
Input Clocks
• Accepts up to 10 differential or CMOS inputs
• Any input frequency from 1 kHz to 1250 MHz
• Per-input activity and frequency monitoring
• Automatic or manual reference switching
• Revertive or nonrevertive switching
• Any input can be a 0.5 Hz to 8 kHz Sync input for
Ref-Sync frequency/phase/time locking
• Any input can be a clock with embedded Sync
• Input phase measurement, 1 ps resolution
• Per-input phase adjustment, 1 ps resolution
Up to 8 DPLLs
• Hitless reference switching
• High-resolution holdover averaging
• Per-DPLL phase adjustment, 1 ps resolution
• Programmable bandwidth, tracking range,
phase-slope limiting, frequency-change limiting
and other advanced features
• Locking to gapped-clock input signals
Output Clocks
• Any frequency 0.5 Hz to 750 MHz
• Each OUTP/N pair can be LVDS, LVPECL, 2xC-
MOS, Low-V , or programmable differential
CM
 2021 Microchip Technology Inc. and its subsidiaries
ZL30641 - ZL30645
Line Card Timing ICs with up to
• In 2xCMOS mode, the P and N pins can be differ-
ent frequencies (e.g. 125 MHz and 25 MHz)
• VDD per output pair, CMOS voltages 1.8V to 3.3V
• Per-synth phase adjustment, 1 ps resolution
• Per-output duty cycle adjustment
• Precise output alignment circuitry and per-output
phase adjustment
• Per-output enable/disable and glitchless start/stop
(stop high or low)
Local Oscillator
• Operates from a single oscillator 9.72 MHz to
400 MHz
• Very-low-jitter applications can connect a TCXO
or OCXO as the stability reference and a low-jitter
XO as the jitter reference
General Features
• Automatic self-configuration at power-up from
internal Flash memory, 7 configurations
• Input-to-output alignment <100 ps
• Fast Ref-Sync locking for frequency and 1PPS
phase alignment with lower-cost oscillator
• Numerically controlled oscillator behavior in each
DPLL and each synthesizer
• Easy-to-configure design requires no external
VCXO or loop filter components
• 5 GPIO pins with many possible behaviors, each
REF can be GPI, each OUT can be GPO
2
• SPI or I C processor Interface
• 1.8V and 3.3V core VDD voltages
• Easy-to-use evaluation/programming software
Applications
• Line card timing ICs for SyncE, SyncE+1588,
routers, switches, OTN, and other carrier-grade
systems
• Wireless base stations (3G, W-CDMA, 4G/LTE,
LTE-A, 5G)
• Remote Radio Unit (RRU), Remote Access Net-
works (RAN), small cells, wireless backhaul, wire-
less repeaters
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