Microchip Technology megaAVR 0 Series Manual page 320

byte is shifted out the interrupt flag is set (IF flag in SPIn.INTFLAGS). The SPI master can operate in two
modes, Normal and Buffered, as explained below.
SS Pin Functionality in Master Mode - Multi-Master Support
In Master mode, the Slave Select Disable bit in Control Register B (SSD bit in SPIn.CTRLB) controls how
the SPI uses the SS line.
• If SSD in SPIn.CTRLB is zero, the SPI can use the SS pin to transition from Master to Slave mode.
This allows multiple SPI masters on the same SPI bus.
• If SSD in SPIn.CTRLB is one, the SPI does not use the SS pin, and it can be used as a regular I/O
pin, or by other peripheral modules.
If SSD in SPIn.CTRLB is zero and the SS is configured as an output pin, it can be used as a regular I/O
pin, or by other peripheral modules, and will not affect the SPI system.
If the SSD bit in SPIn.CTRLB is zero and the SS is configured as an input pin, the SS pin must be held
high to ensure master SPI operation. A low level will be interpreted as another master is trying to take
control of the bus. This will switch the SPI into Slave mode and the hardware of the SPI will perform the
following actions:
1. The master bit in the SPI Control A Register (MASTER bit in SPIn.CTRLA) is cleared and the SPI
system becomes a slave. The direction of the pins will be switched according to
2. The interrupt flag in the Interrupt Flags register (IF flag in SPIn.INTFLAGS) will be set. If the
interrupt is enabled and the global interrupts are enabled the interrupt routine will be executed.
Table 23-2. Overview of the SS Pin Functionality when the SSD Bit in SPIn.CTRLB is Zero
SS Configuration
Input
Output
Note:
If the AVR device is configured for Master mode and it cannot be ensured that the SS pin will stay high
between two transmissions, the status of the Master bit (the MASTER bit in SPIn.CTRLA) has to be
checked before a new byte is written. After the Master bit has been cleared by a low level on the SS line,
it must be set by the application to re-enable the SPI Master mode.
Normal Mode
In Normal mode, the system is single buffered in the transmit direction and double buffered in the receive
direction. This influences the data handling in the following ways:
1. New bytes to be sent cannot be written to the Data register (SPIn.DATA) before the entire transfer
has completed. A premature write will cause corruption of the transmitted data, and the hardware
will set the Write Collision Flag (WRCOL flag in SPIn.INTFLAGS).
2. Received bytes are written to First Receive Buffer register immediately after the transmission is
completed.
3. The First Receive Buffer register has to be read before the next transmission is completed or data
will be lost. This register is read by reading SPIn.DATA.
4. The Transmit Buffer register and Second Receive Buffer register are not used in Normal mode.
©
2018 Microchip Technology Inc.
SS Pin-Level
High
Low
High
Low
Datasheet Preliminary
®
megaAVR
Serial Peripheral Interface (SPI)
Table
Description
Master activated (selected)
Master deactivated, switched to
Slave mode
Master activated (selected)
DS40002015A-page 320
0-Series
23-2.