Microchip Technology megaAVR 0 Series Manual page 225

19.8.7 Interrupt Control Register - Split Mode
Name: INTCTRL
Offset: 0x0A
Reset: 0x00
Property: -
Bit 7
Access
Reset
Bit 6 – LCMP2 Low byte Compare Channel 0 Interrupt Enable
See LCMP0.
Bit 5 – LCMP1 Low byte Compare Channel 1 Interrupt Enable
See LCMP0.
Bit 4 – LCMP0 Low byte Compare Channel 0 Interrupt Enable
Writing LCMPn bit to '1' enables low byte compare interrupt from channel n.
Bit 1 – HUNF High byte Underflow Interrupt Enable
Writing HUNF bit to '1' enables high byte underflow interrupt.
Bit 0 – LUNF Low byte Underflow Interrupt Enable
Writing HUNF bit to '1' enables low byte underflow interrupt.
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2018 Microchip Technology Inc.
6 5
LCMP2 LCMP1
R/W R/W
0 0
16-bit Timer/Counter Type A (TCA)
4 3
LCMP0
R/W
0
Datasheet Preliminary
®
megaAVR 0-Series
2 1
HUNF
R/W
0
DS40002015A-page 225
0
LUNF
R/W
0