Microchip Technology megaAVR 0 Series Manual page 330

23.5.2 Control B
Name: CTRLB
Offset: 0x01
Reset: 0x00
Property: -
Bit 7
BUFEN
Access R/W
Reset 0
Bit 7 – BUFEN Buffer Mode Enable
Writing this bit to '1' enables Buffer mode, meaning two buffers in receive direction, one buffer in transmit
direction, and separate interrupt flags for both transmit complete and receive complete.
Bit 6 – BUFWR Buffer Mode Wait for Receive
When writing this bit to '0' the first data transferred will be a dummy sample.
Value Description
0 One SPI transfer must be completed before the data is copied into the Shift register.
1 When writing to the data register when the SPI is enabled and SS is high, the first write will
go directly to the Shift register.
Bit 2 – SSD Slave Select Disable
When this bit is set and when operating as SPI Master (MASTER=1 in SPIn.CTRLA), SS does not
disable Master mode.
Value Description
0 Enable the Slave Select line when operating as SPI Master
1 Disable the Slave Select line when operating as SPI Master
Bits 1:0 – MODE[1:0] Mode
These bits select the Transfer mode. The four combinations of SCK phase and polarity with respect to the
serial data are shown in the table below. These bits decide whether the first edge of a clock cycle (leading
edge) is rising or falling and whether data setup and sample occur on the leading or trailing edge. When
the leading edge is rising, the SCK signal is low when idle, and when the leading edge is falling, the SCK
signal is high when idle.
Value Name
0x0 0
0x1 1
0x2 2
0x3 3
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2018 Microchip Technology Inc.
6 5
BUFWR
R/W
0
Description
Leading edge: Rising, sample
Trailing edge: Falling, setup
Leading edge: Rising, setup
Trailing edge: Falling, sample
Leading edge: Falling, sample
Trailing edge: Rising, setup
Leading edge: Falling, setup
Trailing edge: Rising, sample
Serial Peripheral Interface (SPI)
4 3
Datasheet Preliminary
®
megaAVR 0-Series
2 1
SSD MODE[1:0]
R/W R/W
0 0
DS40002015A-page 330
0
R/W
0