Arithmetic Logic Unit (Alu); Functional Description - Microchip Technology megaAVR 0 Series Manual

as three 16-bit address pointers for program and data space addressing, enabling efficient address
calculations.
For a summary of all AVR instructions, refer to the Instruction Set Summary.
7.4

Arithmetic Logic Unit (ALU)

The Arithmetic Logic Unit (ALU) supports arithmetic and logic operations between registers, or between a
constant and a register. Also, single-register operations can be executed.
The ALU operates in direct connection with all 32 general purpose registers. Arithmetic operations
between general purpose registers or between a register and an immediate are executed in a single clock
cycle, and the result is stored in the register file. After an arithmetic or logic operation, the Status register
(CPU.SREG) is updated to reflect information about the result of the operation.
ALU operations are divided into three main categories – arithmetic, logical, and bit functions. Both 8- and
16-bit arithmetic are supported, and the instruction set allows for efficient implementation of 32-bit
arithmetic. The hardware multiplier supports signed and unsigned multiplication and fractional format.
7.4.1 Hardware Multiplier
The multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. The hardware multiplier
supports different variations of signed and unsigned integer and fractional numbers:
• Multiplication of signed/unsigned integers
• Multiplication of signed/unsigned fractional numbers
• Multiplication of a signed integer with an unsigned integer
• Multiplication of a signed fractional number with an unsigned one
A multiplication takes two CPU clock cycles.
7.5

Functional Description

7.5.1 Program Flow
After Reset, the CPU will execute instructions from the lowest address in the Flash program memory,
0x0000. The Program Counter (PC) addresses the next instruction to be fetched.
Program flow is supported by conditional and unconditional JUMP and CALL instructions, capable of
addressing the whole address space directly. Most AVR instructions use a 16-bit word format, and a
limited number use a 32-bit format.
During interrupts and subroutine calls, the return address PC is stored on the stack as a word pointer.
The stack is allocated in the general data SRAM, and consequently, the stack size is only limited by the
total SRAM size and the usage of the SRAM. After Reset, the Stack Pointer (SP) points to the highest
address in the internal SRAM. The SP is read/write accessible in the I/O memory space, enabling easy
implementation of multiple stacks or stack areas. The data SRAM can easily be accessed through the
five different addressing modes supported by the AVR CPU.
7.5.2 Instruction Execution Timing
The AVR CPU is clocked by the CPU clock: CLK_CPU. No internal clock division is applied. The figure
below shows the parallel instruction fetches and instruction executions enabled by the Harvard
architecture and the fast-access register file concept. This is the basic pipelining concept enabling up to 1
MIPS/MHz performance with high efficiency.
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2018 Microchip Technology Inc.
Datasheet Preliminary
®
megaAVR 0-Series
AVR CPU
DS40002015A-page 52