Microchip Technology megaAVR 0 Series Manual page 82

32.768 kHz Crystal Oscillator (XOSC32K)
This oscillator supports two input options: Either a crystal is connected to the pins TOSC1 and TOSC2, or
an external clock running at 32 KHz is connected to TOSC1. The input option must be configured by
writing the Source Select bit (SEL) in the XOSC32K Control A register (CLKCTRL.XOSC32KCTRLA).
The XOSC32K is enabled by writing a '1' to its ENABLE bit in CLKCTRL.XOSC32KCTRLA. When
enabled, the configuration of the GPIO pins used by the XOSC32K is overridden as TOSC1, TOSC2 pins.
The Enable bit needs to be set for the oscillator to start running when requested.
The start-up time of a given crystal oscillator can be accommodated by writing to the Crystal Start-up
Time bits (CSUT) in CLKCTRL.XOSC32KCTRLA.
When XOSC32K is configured to use an external clock on TOSC1, the start-up time is fixed to two cycles.
External Clock (EXTCLK)
The EXTCLK is taken directly from the pin. This GPIO pin is automatically configured for EXTCLK if any
peripheral is requesting this clock.
This clock source has a start-up time of two cycles when first requested.
9.3.5 Configuration Change Protection
This peripheral has registers that are under Configuration Change Protection (CCP). In order to write to
these, a certain key must be written to the CPU.CCP register first, followed by a write access to the
protected bits within four CPU instructions.
It is possible to try writing to these registers at any time, but the values are not altered.
The following registers are under CCP:
Table 9-1. CLKCTRL - Registers Under Configuration Change Protection
Register
CLKCTRL.MCLKCTRLB
CLKCTRL.MCLKLOCK
CLKCTRL.XOSC32KCTRLA
CLKCTRL.MCLKCTRLA
CLKCTRL.OSC20MCTRLA
CLKCTRL.OSC20MCALIBA
CLKCTRL.OSC20MCALIBB
CLKCTRL.OSC32KCTRLA
©
2018 Microchip Technology Inc.
Datasheet Preliminary
®
megaAVR 0-Series
Clock Controller (CLKCTRL)
Key
IOREG
IOREG
IOREG
IOREG
IOREG
IOREG
IOREG
IOREG
DS40002015A-page 82