Microchip Technology megaAVR 0 Series Manual page 67

A Flash/EEPROM corruption can be caused by two situations when the voltage is too low:
1. A regular write sequence to the Flash, which requires a minimum voltage to operate correctly.
2. The CPU itself can execute instructions incorrectly when the supply voltage is too low.
See the Electrical Characteristics chapter for Maximum Frequency vs. V
Flash/EEPROM corruption can be avoided by these measures:
• Keep the device in Reset during periods of insufficient power supply voltage. This can be done by
enabling the internal Brown-Out Detector (BOD).
• The voltage level monitor in the BOD can be used to prevent starting a write to the EEPROM close
to the BOD level.
• If the detection levels of the internal BOD don't match the required detection level, an external low
V Reset protection circuit can be used. If a Reset occurs while a write operation is ongoing, the
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write operation will be aborted.
8.3.4 Interrupts
Table 8-2. Available Interrupt Vectors and Sources
Offset Name
0x00 EEREADY
When an interrupt condition occurs, the corresponding interrupt flag is set in the Interrupt Flags register of
the peripheral (NVMCTRL.INTFLAGS).
An interrupt source is enabled or disabled by writing to the corresponding bit in the peripheral's Interrupt
Enable register (NVMCTRL.INTEN).
An interrupt request is generated when the corresponding interrupt source is enabled and the interrupt
flag is set. The interrupt request remains active until the interrupt flag is cleared. See the peripheral's
INTFLAGS register for details on how to clear interrupt flags.
8.3.5 Sleep Mode Operation
If there is no ongoing write operation, the NVMCTRL will enter sleep mode when the system enters sleep
mode.
If a write operation is ongoing when the system enters a sleep mode, the NVM block, the NVM Controller,
and the system clock will remain ON until the write is finished. This is valid for all sleep modes, including
Power-Down Sleep mode.
The EEPROM Ready interrupt will wake up the device only from Idle Sleep mode.
The page buffer is cleared when waking up from Sleep.
8.3.6 Configuration Change Protection
This peripheral has registers that are under Configuration Change Protection (CCP). In order to write to
these, a certain key must be written to the CPU.CCP register first, followed by a write access to the
protected bits within four CPU instructions.
It is possible to try writing to these registers at any time, but the values are not altered.
The following registers are under CCP:
©
2018 Microchip Technology Inc.
Vector Description Conditions
NVM The EEPROM is ready for new write/erase operations.
Datasheet Preliminary
megaAVR
Nonvolatile Memory Controller (NVMCTRL)
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0-Series
DS40002015A-page 67