I/O Memory - Microchip Technology megaAVR 0 Series Manual

Table 5-6. Memory Access in Locked Mode (FUSE.LOCKBIT Invalid)
Memory Section
SRAM
Registers
Flash
EEPROM
USERROW
SIGROW
Other Fuses
Note:
1. Read operations marked No in the tables may appear to be successful, but the data is corrupt.
Hence, any attempt of code validation through the UPDI will fail on these memory sections.
2. In Locked mode, the USERROW can be written blindly using the fuse Write command, but the
current USERROW values cannot be read out.
Important: The only way to unlock a device is a CHIPERASE, which will erase all device
memories to factory default so that no application data is retained.
5.10

I/O Memory

All ATmega3208/3209/4808/4809 I/Os and peripherals are located in the I/O space. The I/O address
range from 0x00 to 0x3F can be accessed in a single cycle using IN and OUT instructions. The Extended
I/O space from 0x0040 - 0x0FFF can be accessed by the LD/LDS/LDD and ST/STS/STD instructions,
transferring data between the 32 general purpose working registers and the I/O space.
I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI
instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC
instructions. Refer to the Instruction Set section for more details.
For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O
memory addresses should never be written.
Some of the interrupt flags are cleared by writing a '1' to them. On ATmega3208/3209/4808/4809 devices,
the CBI and SBI instructions will only operate on the specified bit, and can, therefore, be used on
registers containing such interrupt flags. The CBI and SBI instructions work with registers 0x00 - 0x1F
only.
General Purpose I/O Registers
The ATmega3208/3209/4808/4809 devices provide four General Purpose I/O Registers. These registers
can be used for storing any information, and they are particularly useful for storing global variables and
©
2018 Microchip Technology Inc.
CPU Access
Read Write
Yes Yes
Yes Yes
Yes Yes
Yes No
Yes Yes
Yes No
Yes No
Datasheet Preliminary
®
megaAVR
(1)
UPDI Access
Read Write
No No
No No
No No
No No
No Yes
Yes No
No No
DS40002015A-page 39
0-Series
Memories
(2)