Microchip Technology megaAVR 0 Series Manual page 425

28.5.4 Control D
Name: CTRLD
Offset: 0x03
Reset: 0x00
Property: -
Bit 7
INITDLY[2:0]
Access R/W
Reset 0
Bits 7:5 – INITDLY[2:0] Initialization Delay
These bits define the initialization/start-up delay before the first sample when enabling the ADC or
changing to an internal reference voltage. Setting this delay will ensure that the reference, MUXes, etc.
are ready before starting the first conversion. The initialization delay will also take place when waking up
from deep sleep to do a measurement.
The delay is expressed as a number of CLK_ADC cycles.
Value Name
0x0 DLY0
0x1 DLY16
0x2 DLY32
0x3 DLY64
0x4 DLY128
0x5 DLY256
Other -
Bit 4 – ASDV Automatic Sampling Delay Variation
Writing this bit to '1' enables automatic sampling delay variation between ADC conversions. The purpose
of varying sampling instant is to randomize the sampling instant and thus avoid standing frequency
components in the frequency spectrum. The value of the SAMPDLY bits is automatically incremented by
one after each sample.
When the Automatic Sampling Delay Variation is enabled and the SAMPDLY value reaches 0xF, it wraps
around to 0x0.
Value Name
0 ASVOFF
1 ASVON
Bits 3:0 – SAMPDLY[3:0] Sampling Delay Selection
These bits define the delay between consecutive ADC samples. The programmable Sampling Delay
allows modifying the sampling frequency during hardware accumulation, to suppress periodic noise
sources that may otherwise disturb the sampling. The SAMPDLY field can be also modified automatically
from one sampling cycle to another, by setting the ASDV bit. The delay is expressed as CLK_ADC cycles
and is given directly by the bitfield setting. The sampling cap is kept open during the delay.
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2018 Microchip Technology Inc.
6 5
R/W R/W
0 0
Description
Delay 0 CLK_ADC cycles.
Delay 16 CLK_ADC cycles.
Delay 32 CLK_ADC cycles.
Delay 64 CLK_ADC cycles.
Delay 128 CLK_ADC cycles.
Delay 256 CLK_ADC cycles.
Reserved
Description
The Automatic Sampling Delay Variation is disabled.
The Automatic Sampling Delay Variation is enabled.
Analog-to-Digital Converter (ADC)
4 3
ASDV
R/W R/W
0 0
Datasheet Preliminary
®
megaAVR 0-Series
2 1
SAMPDLY[3:0]
R/W R/W
0 0
DS40002015A-page 425
0
R/W
0