Microchip Technology megaAVR 0 Series Manual page 415

®
megaAVR 0-Series
Analog-to-Digital Converter (ADC)
The event trigger input is edge sensitive. When an event occurs, STCONV in ADCn.COMMAND is set.
STCONV will be cleared when the conversion is complete.
In Free-Running mode, the first conversion is started by writing the STCONV bit to '1' in
ADCn.COMMAND. A new conversion cycle is started immediately after the previous conversion cycle has
completed. A conversion complete will set the RESRDY flag in ADCn.INTFLAGS.
28.3.2.2 Clock Generation
Figure 28-6. ADC Prescaler
ENABLE
Reset
"START"
8-bit PRESCALER
CLK_PER
PRESC
CTRLC
ADC clock source
(CLK_ADC)
The ADC requires an input clock frequency between 50 kHz and 1.5 MHz for maximum resolution. If a
lower resolution than 10 bits is selected, the input clock frequency to the ADC can be higher than 1.5
MHz to get a higher sample rate.
The ADC module contains a prescaler which generates the ADC clock (CLK_ADC) from any CPU clock
(CLK_PER) above 100 kHz. The prescaling is selected by writing to the Prescaler bits (PRESC) in the
Control C register (ADCn.CTRLC). The prescaler starts counting from the moment the ADC is switched
on by writing a '1' to the ENABLE bit in ADCn.CTRLA. The prescaler keeps running as long as the
ENABLE bit is one. The prescaler counter is reset to zero when the ENABLE bit is zero.
When initiating a conversion by writing a '1' to the Start Conversion bit (STCONV) in the Command
register (ADCn.COMMAND) or from an event, the conversion starts at the following rising edge of the
CLK_ADC clock cycle. The prescaler is kept reset as long as there is no ongoing conversion. This
PRESC
assures a fixed delay from the trigger to the actual start of a conversion in CLK_PER cycles as:
StartDelay = + 2
factor
2
Datasheet Preliminary
DS40002015A-page 415
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2018 Microchip Technology Inc.