Instruction Set Summary - Microchip Technology megaAVR 0 Series Manual

30.

Instruction Set Summary

Table 30-1. Status Register (SREG)
Terminology
SREG
C
Z
N
V
S
H
T
I
Table 30-2. Registers and Operands
Operand
Rd
Rr
R
K
k
b
s
X,Y,Z
P
q
UU
SS
SU
Table 30-3. Stack
Terminology
STACK
SP
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2018 Microchip Technology Inc.
Meaning
Status register
Carry flag in status register
Zero flag in status register
Negative flag in status register
Two's complement overflow indicator
N⊕V, for signed tests
Half Carry flag in status register
Transfer bit used by BLD and BST instructions
Global interrupt enable/disable flag
Meaning
Destination (and source) register in the register file
Source register in the register file
Result after instruction is executed
Constant literal or byte data (8-bit)
Constant address data for program counter
Bit in the register file (3-bit)
Bit in the status register (3-bit)
Indirect address register (X=R27:R26, Y=R29:R28
and Z=R31:R30)
I/O port address
Displacement for direct addressing (6-bit)
Unsigned × Unsigned operands
Signed × Signed operands
Signed × Unsigned operands
Meaning
Stack for return address and pushed registers
Stack Pointer to STACK
Datasheet Preliminary
®
megaAVR 0-Series
Instruction Set Summary
DS40002015A-page 472