Microchip Technology megaAVR 0 Series Manual page 249

20.5.5 Interrupt Flags
Name: INTFLAGS
Offset: 0x06
Reset: 0x00
Property: -
Bit 7
Access
Reset
Bit 0 – CAPT Interrupt Flag
This bit is set when an interrupt occurs. The interrupt conditions are dependent on the Counter Mode
(CNTMODE) in TCBn.CTRLB.
This bit is cleared by writing a '1' to it or when the Capture register is read in Capture mode.
Counter Mode
Periodic Interrupt mode
Timeout Check mode
Input Capture on Event mode
Input Capture Frequency
Measurement mode
Input Capture Pulse-Width
Measurement mode
Input Capture Frequency and Pulse-
Width Measurement mode
Single-Shot mode
8-Bit PWM mode
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2018 Microchip Technology Inc.
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Interrupt Flag Behavior
Set when the counter reaches TOP
Set when the counter reaches TOP
Set when an event occurs and the Capture register is loaded,
cleared when Capture is read
Set on an edge when the Capture register is loaded and count
initialized, cleared when Capture is read
Set on an edge when the Capture register is loaded, the previous
edge initialized the count, cleared when Capture is read
Set on second (positive or negative) edge when the counter is
stopped, cleared when Capture is read
Set when counter reaches TOP
Set when the counter reaches CCMPL
16-bit Timer/Counter Type B (TCB)
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Datasheet Preliminary
®
megaAVR 0-Series
2 1
DS40002015A-page 249
0
CAPT
R/W
0