Microchip Technology megaAVR 0 Series Manual page 416

Figure 28-7. Start Conversion and Clock Generation
28.3.2.3 Conversion Timing
A normal conversion takes 13 CLK_ADC cycles. The actual sample-and-hold takes place two CLK_ADC
cycles after the start of a conversion. Start of conversion is initiated by writing a '1' to the STCONV bit in
ADCn.COMMAND. When a conversion is complete, the result is available in the Result register
(ADCn.RES), and the Result Ready interrupt flag is set (RESRDY in ADCn.INTFLAG). The interrupt flag
will be cleared when the result is read from the Result registers, or by writing a '1' to the RESRDY bit in
ADCn.INTFLAG.
Figure 28-8. ADC Timing Diagram - Single Conversion
Cycle Number
ADC clock
ADC enable
STCONV
RESRDY IF
RESH
RESL
Both sampling time and sampling length can be adjusted using the Sample Delay bit field in Control D
(ADCn.CTRLD) and sampling Sample Length bit field in the Sample Control register (ADCn.SAMPCTRL).
Both of these control the ADC sampling time in a number of CLK_ADC cycles. This allows sampling high-
impedance sources without relaxing conversion speed. See register description for further information.
Total sampling time is given by:
SampleTime =
Figure 28-9. ADC Timing Diagram - Single Conversion With Delays
CLK_ADC
ENABLE
STCONV
RES
In Free-Running mode, a new conversion will be started immediately after the conversion completes,
while the STCONV bit is one. The sampling rate R
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2018 Microchip Technology Inc.
CLK_PER
STCONV
CLK_PER/2
CLK_PER/4
CLK_PER/8
2 3
1
sample
2 + SAMPDLY + SAMPLEN
�
CLK_ADC
INITDLY SAMPDLY
(0 – 256 (0 – 15
CLK_ADC cycles) CLK_ADC cycles)
Analog-to-Digital Converter (ADC)
4 6 8 9
5 7
1 2 3 4 5
SAMPLEN
(0 – 31
CLK_ADC cycles)
in free-running mode is calculated by:
S
Datasheet Preliminary
®
megaAVR
10 13
11 12
Result MSB
Result LSB
conversion
complete
6 7 8 9 10 11 12 13
DS40002015A-page 416
0-Series
Result