Microchip Technology megaAVR 0 Series Manual page 340

In the case where the slave is stretching the clock, the master will be forced into a Wait state until the
slave is ready, and vice versa.
24.3.2.7 Arbitration
A master can start a bus transaction only if it has detected that the bus is idle. As the TWI bus is a multi-
master bus, it is possible that two devices may initiate a transaction at the same time. This results in
multiple masters owning the bus simultaneously. This is solved using an arbitration scheme where the
master loses control of the bus if it is not able to transmit a high level on the SDA line. The masters who
lose arbitration must then wait until the bus becomes idle (i.e., wait for a Stop condition) before attempting
to reacquire bus ownership. Slave devices are not involved in the arbitration procedure.
Figure 24-10. TWI Arbitration
DEVICE1_SDA
DEVICE2_SDA
SDA
(wired-AND)
SCL
Figure 24-10 shows an example where two TWI masters are contending for bus ownership. Both devices
are able to issue a Start condition, but DEVICE1 loses arbitration when attempting to transmit a high level
(bit 5) while DEVICE2 is transmitting a low level.
Arbitration between a repeated start condition and a data bit, a Stop condition and a data bit, or a
repeated Start condition and a Stop condition are not allowed and will require special handling by
software.
24.3.2.8 Synchronization
A clock synchronization algorithm is necessary for solving situations where more than one master is
trying to control the SCL line at the same time. The algorithm is based on the same principles used for
the clock stretching previously described.
competing for control over the bus clock. The SCL line is the wired-AND result of the two masters clock
outputs.
©
2018 Microchip Technology Inc.
DEVICE1 Loses arbitration
bit 7
S
Figure 24-11 shows an example where two masters are
Datasheet Preliminary
megaAVR
Two-Wire Interface (TWI)
bit 6 bit 5 bit 4
DS40002015A-page 340
®
0-Series