Microchip Technology megaAVR 0 Series Manual page 120

Generator Event
RTC Overflow
Compare Match
PIT RTC Prescaled
clock
CCL-LUT
AC Comparator result
ADC Result ready
Window compare
match
PORT Pin input
USART USART Baud
clock
SPI SPI Master clock
TCA Overflow
Underflow in split
mode
Compare match
ch 0
Compare match
ch 1
Compare match
ch 2
TCB Compare match,
timeout or when
counting
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2018 Microchip Technology Inc.
Generating Length of event
Clock Domain
synchronized to
CLK_PDI
CLK_RTC Pulse: 1 * CLK_RTC
CLK_RTC Pulse: 1 * CLK_RTC
CLK_RTC Pulse: ≥1 * CLK_RTC
Asynchronous Depends on CCL
configuration
Asynchronous Level: Typically ≥1 us
CLK_ADC Pulse: 1 * CLK_PER
CLK_ADC Pulse: 1 * CLK_PER
Asynchronous Level: Externally
controlled
TXCLK Pulse: ≥2 * CLK_PER
SCK Pulse: ≥2 * CLK_PER
CLK_PER Pulse: 1 * CLK_PER
CLK_PER Pulse: 1 * CLK_PER
CLK_PER Pulse: 1 * CLK_PER
CLK_PER Pulse: 1 * CLK_PER
CLK_PER Pulse: 1 * CLK_PER
CLK_PER Pulse: ≥1 * CLK_PER
Datasheet Preliminary
®
megaAVR 0-Series
Event System (EVSYS)
Constraints for
synchronous user
to guarantee that the
event is seen by the user
None
Clock source used for
CCL must be slower or
equal to CLK_PER or
input signals to CCL are
stable for at least Tclk_per
Frequency of input signals
to AC must be ≤fclk_per
to guarantee that the
event is seen by the
synchronous user
None
Input signal must be
stable for longer than
fclk_per
None
None
None
None
DS40002015A-page 120