Microchip Technology megaAVR 0 Series Manual page 345

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megaAVR 0-Series
Two-Wire Interface (TWI)
Case M2: Address Packet Transmit Complete - Address not Acknowledged by Slave
If no slave device responds to the address, the Master Write Interrupt Flag (WIF in TWIn.MSTATUS) and
the Master Received Acknowledge Flag (RXACK in TWIn.MSTATUS) are set. The RXACK flag reflects
the physical state of the ACK bit (i.e.< no slave did pull the ACK bit low). The clock hold is active at this
point, preventing further activity on the bus.
Case M3: Address Packet Transmit Complete - Direction Bit Cleared
If the master receives an ACK from the slave, the Master Write Interrupt Flag (WIF in TWIn.MSTATUS) is
set and the Master Received Acknowledge Flag (RXACK in TWIn.MSTATUS) is cleared. The clock hold
is active at this point, preventing further activity on the bus.
Case M4: Address Packet Transmit Complete - Direction Bit Set
If the master receives an ACK from the slave, the master proceeds to receive the next byte of data from
the slave. When the first data byte is received, the Master Read Interrupt Flag (RIF in TWIn.MSTATUS) is
set and the Master Received Acknowledge Flag (RXACK in TWIn.MSTATUS) is cleared. The clock hold
is active at this point, preventing further activity on the bus.
Transmitting Data Packets
Assuming the above M3 case, the master can start transmitting data by writing to the Master Data
(TWIn.MDATA) register, which will also clear the Write Interrupt Flag (WIF). During data transfer, the
master is continuously monitoring the bus for collisions and errors. The WIF will be set anew after the full
data packet transfer has been completed, the arbitration is lost (ARBLOST), or if a bus error (BUSERR)
occur during the transfer.
The WIF, ARBLOST, and BUSERR flags together with the value of the last acknowledge bit (RXACK) are
all located in the Master Status (TWIn.MSTATUS) register. The RXACK status is only valid if WIF is set
and not valid if ARBLOST or BUSERR is set, so the software driver must check this first. The RXACK will
be zero if the slave responds to the data with an ACK, which indicates that the slave is ready for more
data (if any). A NACK received from the slave indicates that the slave is not able to or does not need to
receive more data after the last byte. The master must then either issue a Repeated Start (Sr) (write a
new value to TWIn.MADDR) or complete the transaction by issuing a Stop condition (MCMD field in
TWIn.MCTRLB = MCMD_STOP).
In I²C slaves, the use of Repeated Start conditions (Sr) entirely depends on how each slave interprets the
protocol. In SMBus slaves, interpretation of a Repeated Start condition is defined by higher levels of the
protocol specification.
Receiving Data Packets
Assuming case M4 above, the master has already received one byte from the slave. The master read
interrupt flag is set, and the master must prepare to receive new data. The master must respond to each
byte with ACK or NACK. A NACK response might not be successfully executed, as arbitration can be lost
during the transmission. If a collision is detected, the master loses arbitration and the arbitration lost flag
is set.
Quick Command Mode
With Quick Command enabled (QCEN in TWIn.MCTRLA), the R/W# bit of the slave address denotes the
command. This is a SMBus specific command where the R/W bit may be used to simply turn a device
function ON or OFF, or enable/disable a low-power Standby mode. There is no data sent or received.
After the master receives an acknowledge from the slave, either RIF or WIF flag in TWIn.MSTATUS will
be set depending on the polarity of R/W. When either RIF or WIF flag is set after issuing a Quick
Command, the TWI will accept a stop command through writing the CMD bits in TWIn.MCTRLB.
Datasheet Preliminary
DS40002015A-page 345
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2018 Microchip Technology Inc.